74LS92 Divide By 12 Counter (7492 IC) DIP-14 Package
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74LS92 Divide By 12 Counter (7492 IC) DIP-14 Package

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₹ 65.00
(Excluding Tax : ₹ 55.08 + GST 18% : ₹ 9.92)
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The SN54/74LS92 is high-speed 4-bit ripple type counters partitioned into two sections. One counter has a divide-by-two section and another counter has a divide-by-six section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form modulo-12 counters. The counter have a 2-input gated Master Reset (Clear).

Features

  • Low Power Consumption - 45mW
  • High Count Rates - 42MHz
  • Input Clamp Diodes Limit High Speed Termination Effects
  • Low Power Dissipation
  • Standard TTL Switching Voltages

Working

Modulo 12, Divide-By-Twelve Counter — The CP1 input must be externally connected to the Q0 output. The CP0 input receives the incoming count and Q3 produces a symmetrical divide-by-twelve square wave output. B.

Divide-By-Two and Divide-By-Six Counter —No external interconnections are required. The first flip-flop is used as a binary element for the divide-by-two function. The CP1 input is used to obtain divide-by-three operation at the Q1 and Q2 outputs and divide-by-six operation at the Q3 output.

The SN54/74LS92 is high-speed 4-bit ripple type counters partitioned into two sections. One counter has a divide-by-two section and another counter has a divide-by-six section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form modulo-12 counters. The counter have a 2-input gated Master Reset (Clear).

Features

  • Low Power Consumption - 45mW
  • High Count Rates - 42MHz
  • Input Clamp Diodes Limit High Speed Termination Effects
  • Low Power Dissipation
  • Standard TTL Switching Voltages

Working

Modulo 12, Divide-By-Twelve Counter — The CP1 input must be externally connected to the Q0 output. The CP0 input receives the incoming count and Q3 produces a symmetrical divide-by-twelve square wave output. B.

Divide-By-Two and Divide-By-Six Counter —No external interconnections are required. The first flip-flop is used as a binary element for the divide-by-two function. The CP1 input is used to obtain divide-by-three operation at the Q1 and Q2 outputs and divide-by-six operation at the Q3 output.

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